BREAM & LAANAIA
155 cours Berriat - 38000 Grenoble
Tél 04 76 70 94 73 - Contact mail
DIRECTOR OF HARDWARE ENGINEERING
Our customer is a fabless semiconductor company providing dedicated neural chips powered by MRAM-based innovative architectures making AI at the edge more efficient and powerful. It’s providing full solutions optimized across the spectrum of performance, power and area to help customers solve their design challenges in a wide range of markets: mobile, wearable, IoT...The company is offering as well MRAM memory design services for embedded and standalone applications. We are actively seeking a Director of Hardware Engineering (M/F).
The candidate will define, co-define, the MRAM(magnetic memory)-based AI chip strategy and architecture, involved in the purchase or the definition and design of digital blocks (CPU, deep neural networks, IO interfaces, microarchitectures (MAC operations), memory controllers…) on the most advanced CMOS technologies. He will structure and oversee the digital team (front-end, software, back-end, including external contractors), managing the projects from specs to tape-out, up to silicon validation, packaging, and tests. He will be mentoring, assisting, and supporting other team members in technical issues ; he is involved in task planning, work allocation, and hiring process. He will have to track deliveries, prioritize project tasks, and identify risks.
MS/PhD degree in Electrical Engineering with 12+ years’ experience (mainly industry/startup) in low power chips/products design with a strong focus on DNN (Deep Neural Network), CPU, DSP or MCU.
Must have successful tape-out experiences in related field, providing to the team technical leadership and support to develop low power chips/products from concept/specs to tape-out.
Deep experience in architecting and designing low power products, co-processors, expertise in low-power design techniques and low-power design flows. Experience in cache/memory subsystem definition, design, and optimization, eNVM memory controllers, BIST/ECC, advanced bus architectures.
Strong technical backgrounds in test (BIST, scan…), debug, verification, functional test patterns for production test program to validate silicon on tester. Familiar with latest verification techniques (SV/UVM/UPF…).
Experience in using deep sub-micron technologies (40nm and below), FDSOI, FinFET.
Work in a dynamic, team-oriented environment and able to multi-task. Be an effective risk-taker, like challenges, be comfortable with unforeseen circumstances.
Willingness and ability to learn new subjects, find solutions for challenging issues, and apply creativity to drive innovation.